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(a) Bus release signal (REL)
(b) Command signal (CMD)
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CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries)
The bus release signal is generated when the SCK0 line is in high level (a serial clock is not output) and
the SB0 (SB1) line changes from low level to high level.
The bus release signal is output by the master.
The bus release signal indicates that the master will send the address to the slave. The slave contains
hardware to detect the bus release signal.
Caution The bus release signal is acknowledged when the SCK0 line is in high level, and the SB0
(SB1) line changes from low level to high level. Thus, if the timing at which bus changes
deviates due to effects such as board capacity, it may be determined as the bus release
signal even if data is sent. Therefore perform wiring carefully.
The command signal is generated when the SCK0 line is in high level (a serial clock is not output) and the
SB0 (SB1) line changes from high level to low level.
The command signal is output by the master.
The command signal indicates that the master will send the command to the slave (However, the command
signal following the bus release signal indicates that address will be sent).
The slave contains hardware to detect the command signal.
Caution The command signal is acknowledged when the SCK0 line is in high level, and the SB0
(SB1) line changes from high level to low level. Thus, if the timing at which bus changes
deviates due to effects such as board capacity, it may be determined as the command
signal even if data is sent. Therefore perform wiring carefully.
Figure 15-13. Bus Release Signal
SCK0
"H"
SB0 (SB1)
Figure 15-14. Command Signal
SCK0
"H"
SB0 (SB1)
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