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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
Figure 16-45. Data Transmission from Master to Slave
(Both Master and Slave Selected 9-Clock Wait) (1/3)
Master device operation
Write SIO0
COI
ACKD
CMDD
"L"
RELD
CLD
P27
"H"
"L"
WUP
"L"
ACKE
CMDT
"L"
RELT
CLC
"L"
WREL
"L"
SIC
INTCSI0
Transfer line
SCL
SDA0 (SDA1)
Slave device operation
Write SIO0
COI
ACKD
CMDD
"L"
RELD
CLD
P27
WUP
ACKE
"H"
"L"
CMDT
"L"
RELT
"L"
CLC
"L"
WREL
"L"
SIC
INTCSI0
(a) Start Condition to Address
SIO0 ← Address
1
2
3
4
5
6
7
A6
A5 A4 A3 A2 A1 A0 W ACK
SIO0 ← Address
8
9
1
2
3
D7
D6
D5
SIO0 ← FFH
4
5
D4
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