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(f) Wait signal (WAIT)
master device
slave device
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SDA0 (SDA1)
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
The wait signal is output by a slave device to inform the master device that the slave device is in wait state
due to preparing for transmitting or receiving data.
The slave device notifies the master device about the wait state by keeping the SCL pin low.
When the wait state is released, the master device can start the next transfer. For the releasing operation
of slave devices, see section 16.4.6 Cautions on use of I
SCL of
6
7
SCL of
SCL
D2
D1
SCL of
6
master device
SCL of slave device
SCL
SDA0 (SDA1)
D2
Figure 16-43. Wait Signal
(a) Wait of 8 Clock Cycles
Slave device drives low, though
master device returns to Hi-Z state.
8
9
D0
ACK
Output by manipulating ACKT
(b) Wait of 9 Clock Cycles
7
8
9
D1
D0
ACK
Output based on the value set in ACKE in advance
2
C bus mode.
No wait is inserted after 9th clock cycle.
(and before master device starts next transfer.)
1
2
3
4
D7
D6
D5
D4
Slave device drives low, though
master device returns to Hi-Z state.
1
2
D7
D6
3
D5
383
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