NEC 78014Y Series User Manual page 391

(5) Pin configurations
The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below.
(a) SCL ......................... Pin for serial clock input/output.
(b) SDA0 (SDA1) ......... Serial data input/output dual-function pin.
Both serial clock and serial data bus require the external pull-up resistors to be output by N-ch open drain.
Clock output
(Clock input)
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Caution Because the N-ch open-drain output must be set to high-impedance at the time of data
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
<1> Master ............. N-ch open-drain output
<2> Slave ............... Schmitt input
Uses N-ch open-drain output and Schmitt-input buffers for both master and slave
devices.
Master device
Data output
Data input
reception, write FFH to the serial I/O shift register 0 (SIO0) in advance. However, when wake-
up function is used (that is, bit 5 (WUP) of serial operating mode register 0 (CSIM0) is set), do
not write FFH to SIO0 before data reception. Without writing FFH to SIO0, the N-ch open-drain
output is always high-impedance state.
Figure 16-44. Pin Configuration
V
DD
SCL
V
DD
SDA0 (SDA1)
SDA0 (SDA1)
Slave device
SCL
(Clock output)
Clock input
Data output
Data input
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