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Instruc- Mnemonic
tion
Group
8-bit
Ope-
ration
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Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Operands
SUBC
A, #byte
saddr, #byte
A, r
Note 3
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, [HL+B]
A, [HL+C]
AND
A, #byte
saddr, #byte
Note 3
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, [HL+B]
A, [HL+C]
OR
A, #byte
saddr, #byte
A, r
Note 3
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, [HL+B]
A, [HL+C]
register (PCC).
2. Clock indicates when a program is in the internal ROM area.
3. n is the number of waits when the external memory expansion area is read.
CHAPTER 23 INSTRUCTION SET
Byte
Clock
Note 1
Note 2
2
8
—
3
12
16
2
8
—
2
8
—
2
8
10
3
16
18 + 2n
1
8
10 + 2n
2
16
18 + 2n
2
16
18 + 2n
2
16
18 + 2n
2
8
—
3
12
16
2
8
—
2
8
—
2
8
10
3
16
18 + 2n
1
8
10 + 2n
2
16
18 + 2n
2
16
18 + 2n
2
16
18 + 2n
2
8
—
3
12
16
2
8
—
2
8
—
2
8
10
3
16
18 + 2n
1
8
10 + 2n
2
16
18 + 2n
2
16
18 + 2n
2
16
18 + 2n
Operation
A, CY ← A–byte–CY
(saddr), CY ← (saddr)–byte–CY
A, CY ← A–r–CY
r, CY ← r–A–CY
A, CY ← A–(saddr)–CY
A, CY ← A–(addr16)–CY
A, CY ← A–(HL)–CY
A, CY ← A–(HL+byte)–CY
A, CY ← A–(HL+B)–CY
A, CY ← A–(HL+C)–CY
A ← A∧byte
(saddr) ← (saddr) ∧byte
A ← A∧r
r ← r∧A
A ← A∧ (saddr)
A ← A∧ (addr16)
A ← A∧ (HL)
A ← A∧ (HL+byte)
A ← A∧ (HL+B)
A ← A∧ (HL+C)
A ← A∨byte
(saddr) ← (saddr) ∨byte
A ← A∨r
r ← r∨A
A ← A∨ (saddr)
A ← A∨ (addr16)
A ← A∨ (HL)
A ← A∨ (HL+byte)
A ← A∨ (HL+B)
A ← A∨ (HL+C)
) selected by processor clock control
CPU
Flag
Z
AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
509
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