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When the sampling INTP0 input level is active twice in succession, the noise eliminator sets the interrupt request
flag (PIF0) to 1. Figure18-7 shows noise eliminator input/output timing.
Figure 18-7. Noise Eliminator Input/Output Timing (when rising edge is detected)
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CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION
(a) When input is less than the sampling cycle (t
Sampling Clock
INTP0
"L"
PIF0
Because INTP0 level is not high level in sampling,
PIF0 output remains at low level.
(b) When input is equal to or twice the sampling cycle (t
Sampling Clock
INTP0
PIF0
Because sampling INTP0 level is high level twice in succession in <2>,
PIF0 flag is set to 1.
(c) When input is twice or more than the sampling cycle (t
Sampling Clock
INTP0
PIF0
When INTP0 level is high level twice in succession,
PIF0 flag is set to 1.
t
SMP
t
SMP
<1>
<2>
t
SMP
)
SMP
)
SMP
)
SMP
457
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