NEC 78014Y Series User Manual page 354

(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SBIC to 00H.
Symbol <7>
SBIC BSYE ACKD ACKE
R/W RELT
R/W CMDT
R RELD
Clear Conditions (RELD = 0)
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in address
reception (only if WUP = 1)
• When CSIE0 = 0
• When RESET input is applied
R CMDD
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Clear Conditions (CMDD = 0)
• When transfer start instruction is executed
• When bus release signal (REL) is detected in the SBI mode
• When CSIE0 = 0
• When RESET input is applied
R/W ACKT
Note Bits 2, 3 and 6 (RELD, CMDD, and ACKD) are Read-Only bits.
Remarks 1.
2.
354
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
<6> <5> <4> <3>
ACKT CMDD RELD CMDT
Use for bus release signal output when the SBI mode is used.
When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
Use for command signal output when the SBI mode is used.
When CMDT = 1, SO latch is cleared to 0. After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
Bus Release Detection
Command Detection
When the SBI mode is used, acknowledge signal is output in synchronization with the falling edge of SCK0
clock immediately after execution of the instruction to be set to 1, and after acknowledge signal output,
automatically cleared to 0. Used as ACKE = 0.
Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
Zeros will be returned form bits 0, 1, and 4 (or RELT, CMDT, ACKT, respectively) if users read these
bits after data setting is completed.
CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
<2> <1> <0> Address
RELT FF61H
Set Conditions (RELD = 1)
• When bus release signal (REL) is detected in the SBI mode
Set Conditions (CMDD = 1)
• When command signal (CMD) is detected in the SBI mode
When Reset R/W
Note
00H R/W
(continued)