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Serial Operating Mode Register 0
CSIE0 COI WUP CSIM
Control Circuit
SI0/SB0/P25
PM25
Output
Control
SO0/SB1/P26
PM26
Output
Control
CLD
SCK0/P27
PM27
Output
Control
Remark
Output control performs selection between CMOS output and N-ch open-drain output.
Figure 15-3. Serial Interface Channel 0 Block Diagram
Internal Bus
CSIM
CSIM
CSIM
CSIM
Slave Address
00
04
03
02
01
Register (SVA)
Match
Serial I/O Shift
Selector
Register 0 (SIO0)
P25
Output Latch
Selector
P26 Output Latch
P27
Output Latch
Serial Bus Interface
Control Register
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
SVAM
CLR SET
D
Q
Busy/
Acknowledge
Output
Circuit
Bus Release/
ACKD
Command/
CMDD
Acknowledge
RELD
WUP
Detector
Interrupt
Request
Serial Clock
Signal
Generator
Counter
Serial Clock
Selector
Control Circuit
CSIM00
CSIM01
CLD SIC SVAM
Interrupt Timing
Specification Register
Internal Bus
INTCSI0
TO2
Selector
f
/2
2
to f
/2
9
X
X
CSIM00
4
CSIM01
TCL33 TCL32 TCL31 TCL30
Timer Clock
Select Register 3
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