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(5) Sampling clock select register (SCS)
This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled
data reception is carried out using INTP0, digital noise is removed with sampling clocks.
SCS is set with an 8-bit memory manipulation instruction.
RESET input sets SCS to 00H.
Symbol
7
SCS
0
N+1
Caution
f
/2
X
peripheral hardware. f
Remarks 1. N: Value (N = 0 to 4) at bits 0 to 2 (PCC0 to PCC2) of processor clock control register (PCC)
2. f
X
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3. Values in parentheses apply to operation with f
456
CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION
Figure 18-6. Sampling Clock Select Register Format
6
5
4
3
0
0
0
0
is a clock to be supplied to the CPU and f
N+1
/2
stops in the HALT mode.
X
: Main system clock oscillation frequency
2
1
0
Address
0
SCS1
SCS0
FF47H
SCS1
SCS0
0
0
1
1
6
/2
and f
X
= 10.0 MHz.
X
When Reset
R/W
00H
R/W
INTP0 Sampling Clock Selection
N+1
0
f
/2
X
1
Setting prohibited
0
f
/2
6
(156 kHz)
X
7
1
f
/2
(78.1 kHz)
X
7
/2
are clocks to be supplied to the
X
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