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16-19 Data .................................................................................................................................................. 350
16-20 Acknowledge Signal .......................................................................................................................... 351
16-21 Busy Signal, Ready Signal ................................................................................................................ 352
16-22 RELT, CMDT, RELD and CMDD Operations (Master) ..................................................................... 357
16-23 RELD and CMDD Operations (Slave) ............................................................................................... 357
16-24 ACKT Operation ................................................................................................................................ 358
16-25 ACKE Operations .............................................................................................................................. 359
16-26 ACKD Operations ............................................................................................................................. 360
16-27 BSYE Operation ................................................................................................................................ 360
16-28 Pin Configuration .............................................................................................................................. 363
16-29 Address Transmission from Master Device to Slave Device (WUP = 1) .......................................... 366
16-30 Command Transmission from Master Device to Slave Device ......................................................... 367
16-31 Data Transmission from Master Device to Slave Device .................................................................. 368
16-32 Data Transmission from Slave Device to Master Device .................................................................. 369
16-33 Example of Serial Bus Configuration with 2-Wire Serial I/O ............................................................. 372
16-34 2-Wire Serial I/O Mode Timings ........................................................................................................ 376
16-35 RELT and CMDT Operations ............................................................................................................ 377
16-36 Serial Bus Configuration Example Using I 2 C Bus ............................................................................ 378
16-37 I 2 C Bus Serial Data Transfer Timing ................................................................................................ 379
16-38 Start Condition .................................................................................................................................. 380
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16-39 Address ............................................................................................................................................. 381
16-40 Transfer Direction Specification ........................................................................................................ 381
16-41 Acknowledge Signal .......................................................................................................................... 382
16-42 Stop Condition .................................................................................................................................. 382
16-43 Wait Signal ........................................................................................................................................ 383
16-44 Pin Configuration .............................................................................................................................. 391
16-45 Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) .............. 393
16-46 Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) .............. 396
16-47 Start Condition Output ...................................................................................................................... 400
16-48 Slave Wait Release (Transmission) .................................................................................................. 401
16-49 Slave Wait Release (Reception) ....................................................................................................... 402
16-50 SCK0/SCL/P27 Pin Configuration ..................................................................................................... 406
16-51 SCK0/SCL/P27 Pin Configuration ..................................................................................................... 407
16-52 SCL Signal Logic .............................................................................................................................. 407
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
Serial Interface Channel 1 Block Diagram ........................................................................................ 411
Timer Clock Select Register 3 Format .............................................................................................. 414
Serial Operating Mode Register 1 Format ........................................................................................ 415
Automatic Data Transmit/Receive Control Register Format ............................................................. 417
3-Wire Serial I/O Mode Timings ........................................................................................................ 420
Circuit of Switching in Transfer Bit Order .......................................................................................... 421
Basic Transmit/Receive Mode Operation Timings ............................................................................ 426
Basic Transmit/Receive Mode Flowchart .......................................................................................... 427
Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) ......... 428
LIST OF FIGURES (5/7)
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