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(6) Sampling clock select register (SCS)
This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote
controlled reception is carried out using INTP0, digital noise is removed with sampling clock.
SCS is set with an 8-bit memory manipulation instruction.
RESET input sets SCS value to 00H.
Symbol
SCS
Caution
Remarks 1. N: Value set in bit 0 to bit 2 (PCC0 to PCC2) of the processor clock control register (PCC) (N = 0
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER
Figure 8-9. Sampling Clock Select Register Format
7
6
5
4
0
0
0
0
N+1
f
/2
is the clock supplied to the CPU, and f
X
N+1
hardware. f
/2
is stopped in HALT mode.
X
to 4)
2. f
: Main system clock oscillation frequency
X
3. Values in parentheses apply to operation with f
3
2
1
0
0
0
SCS1
SCS0
SCS1
6
/2
X
= 10.0 MHz.
X
Address
When Reset
R/W
FF47H
00H
R/W
SCS0
INTP0 Sampling Clock Selection
0
0
f
/2
N+1
X
0
1
Setting prohibited
1
0
f
/2
6
(156 kHz)
X
1
1
f
/2
7
(78.1 kHz)
X
7
and f
/2
are clocks supplied to peripheral
X
185
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