Table of Contents
Advertisement
Instruc- Mnemonic
tion
Group
8-bit
data
trans-
fer
16-bit
data
trans-
fer
www.DataSheet4U.com
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except r = A
4. Only when rp = BC, DE or HL
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Operands
Note 3
XCH
A, r
A, saddr
A, sfr
A, !addr16
A, [DE]
A, [HL]
A, [HL+byte]
A, [HL+B]
A, [HL+C]
MOVW
rp, #word
saddrp, #word
sfrp, #word
AX, saddrp
saddrp, AX
AX, sfrp
sfrp, AX
Note 4
AX, rp
Note 4
rp, AX
AX, !addr16
!addr16, AX
XCHW
AX, rp
Note 4
register (PCC).
2. Clock indicates when a program is in the internal ROM area.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
CHAPTER 23 INSTRUCTION SET
Byte
Clock
Note 1
Note 2
1
4
—
2
8
12
2
—
12
20 + 2n + 2m A ↔ (addr16)
3
16
12 + 2n + 2m A ↔ (DE)
1
8
12 + 2n + 2m A ↔ (HL)
1
8
20 + 2n + 2m A ↔ (HL+byte)
2
16
20 + 2n + 2m A ↔ (HL+B)
2
16
20 + 2n + 2m A ↔ (HL+C)
2
16
3
12
—
4
16
20
4
—
20
2
12
16
2
12
16
2
—
16
2
—
16
1
8
—
1
8
—
3
20
24 + 4n
3
20
24 + 4m
1
8
—
Operation
A ↔ r
A ↔ (saddr)
A ↔ sfr
rp ← word
(saddrp) ← word
sfrp ← word
AX ← (saddrp)
(saddrp) ← AX
AX ← sfrp
sfrp ← AX
AX ← rp
rp ← AX
AX ← (addr16)
(addr16) ← AX
AX ↔ rp
) selected by processor clock control
CPU
Flag
Z
AC CY
507
Advertisement
Table of Contents
