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Figure No.
7-4
External Circuit of Main System Clock Oscillator .............................................................................. 160
7-5
External Circuit of Subsystem Clock Oscillator ................................................................................. 160
7-6
Examples of Resonator with Bad Connection ................................................................................... 161
7-7
Main System Clock Stop Function .................................................................................................... 165
7-8
System Clock and CPU Clock Switching .......................................................................................... 169
8-1
16-Bit Timer/Event Counter (Timer Mode) Block Diagram ............................................................... 174
8-2
16-Bit Timer/Event Counter (PWM Mode) Block Diagram ................................................................ 175
8-3
16-Bit Timer/Event Counter Output Control Circuit Block Diagram .................................................. 176
8-4
Timer Clock Select Register 0 Format .............................................................................................. 179
8-5
16-Bit Timer Mode Control Register Format ..................................................................................... 181
8-6
16-Bit Timer Output Control Register Format ................................................................................... 182
8-7
Port Mode Register 3 Format ............................................................................................................ 183
8-8
External Interrupt Mode Register Format .......................................................................................... 184
8-9
Sampling Clock Select Register Format ........................................................................................... 185
8-10
Interval Timer Configuration Diagram ............................................................................................... 186
8-11
Interval Timer Operation Timings ...................................................................................................... 187
8-12
Example of D/A Converter Configuration with PWM Output ............................................................. 189
8-13
TV Tuner Application Circuit Example .............................................................................................. 189
8-14
Configuration Diagram for Pulse Width Measurement by Free-Running Counter ............................ 190
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8-15
Timing of Pulse Width Measurement Operation by Free-Running Counter
(with Both Edges Specified) .............................................................................................................. 191
8-16
Timing of Pulse Width Measurement Operation by Means of Restart
(with Both Edges Specified) .............................................................................................................. 192
8-17
External Event Counter Configuration Diagram ................................................................................ 193
8-18
External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 194
8-19
Square-Wave Output Operation Timings .......................................................................................... 195
8-20
16-Bit Timer Register Start Timings .................................................................................................. 196
8-21
Timings after Change of Compare Register during Timer Count Operation ..................................... 196
8-22
Capture Register Data Retention Timings ........................................................................................ 197
8-23
OVF0 Flag Operation Timing ............................................................................................................ 198
9-1
8-Bit Timer/Event Counter Block Diagram ........................................................................................ 205
9-2
8-Bit Timer/Event Counter Output Control Circuit 1 Block Diagram ................................................. 206
9-3
8-Bit Timer/Event Counter Output Control Circuit 2 Block Diagram ................................................. 206
9-4
Timer Clock Select Register 1 Format .............................................................................................. 208
9-5
8-Bit Timer Mode Control Register Format ....................................................................................... 209
9-6
8-Bit Timer Output Control Register Format ..................................................................................... 210
9-7
Port Mode Register 3 Format ............................................................................................................ 211
9-8
Interval Timer Operation Timings ...................................................................................................... 212
9-9
External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 214
9-10
Square-Wave Output Operation Timings .......................................................................................... 215
9-11
Interval Timer Operation Timings ...................................................................................................... 216
9-12
External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 218
24
LIST OF FIGURES (2/7)
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