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Figure No.
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Pin Input/Output Circuit List ..............................................................................................................
Pin Input/Output Circuit List ..............................................................................................................
Memory Map ( µ PD78011B, 78011BY) .............................................................................................
Memory Map ( µ PD78012B, 78012BY) .............................................................................................
Memory Map ( µ PD78013, 78013Y) ..................................................................................................
Memory Map ( µ PD78014, 78014Y) ..................................................................................................
Memory Map ( µ PD78P014, 78P014Y) .............................................................................................
Program Counter Configuration ........................................................................................................ 102
Program Status Word Configuration ................................................................................................. 102
Stack Pointer Configuration .............................................................................................................. 104
Data to be Saved to Stack Memory .................................................................................................. 105
Data to be Reset from Stack Memory ............................................................................................... 105
General Register Configuration ........................................................................................................ 107
Data Memory Addressing ( µ PD78011B, 78011BY) .......................................................................... 115
Data Memory Addressing ( µ PD78012B, 78012BY) .......................................................................... 116
Data Memory Addressing ( µ PD78013, 78013Y) .............................................................................. 117
Data Memory Addressing ( µ PD78014, 78014Y) .............................................................................. 118
Data Memory Addressing ( µ PD78P014, 78P014Y) .......................................................................... 119
Port Types ......................................................................................................................................... 129
P00 Block Diagram ........................................................................................................................... 134
P01 to P03 Block Diagrams .............................................................................................................. 135
P04 Block Diagram ........................................................................................................................... 135
P10 to P17 Block Diagrams .............................................................................................................. 136
P20, P21, P23 to P26 Block Diagrams ( µ PD78014 Subseries) ........................................................ 137
P22 and P27 Block Diagrams ( µ PD78014 Subseries) ..................................................................... 138
P20, P21, P23 to P26 Block Diagrams ( µ PD78014Y Subseries) ..................................................... 139
P22 and P27 Block Diagrams ( µ PD78014Y Subseries) ................................................................... 140
P30 to P37 Block Diagrams .............................................................................................................. 141
P40 to P47 Block Diagrams .............................................................................................................. 142
Block Diagram of Falling Edge Detector ........................................................................................... 142
P50 to P57 Block Diagrams .............................................................................................................. 143
P60 to P63 Block Diagrams .............................................................................................................. 145
P64 to P67 Block Diagrams .............................................................................................................. 145
Port Mode Register Format ............................................................................................................... 148
Pull-Up Resistor Option Register Format .......................................................................................... 149
Memory Expansion Mode Register Format ...................................................................................... 150
Key Return Mode Register Format ................................................................................................... 151
Clock Generator Block Diagram ....................................................................................................... 156
Feedback Resistor of Subsystem Clock ........................................................................................... 157
Processor Clock Control Register Format ........................................................................................ 158
LIST OF FIGURES (1/7)
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