NEC 78014Y Series User Manual page 442

(c) Bit shift detection by busy signal
During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because
noise is superimposed on the serial clock signal output by the master device. Unless the strobe control option
is used at this time, the bit shift affects transmission of the next byte. In this case, the master can detect
the bit shift by checking the busy signal during transmission by using the busy control option.
A bit shift is detected by using the busy signal as follows:
The slave outputs the busy signal after the rising of the eighth serial clock during data transmission/reception
(to not keep transmission/reception waiting by the busy signal at this time, make the busy signal inactive
within 2 clocks).
The master samples the busy signal in synchronization of the falling of the leading side of the serial clock.
If a bit shift does not occur, all the eight serial clocks that have been sampled are inactive. If the sampled
serial clocks are active, it is assumed that a bit shift has occurred, and error processing is executed (by setting
bit 4 (ERR) of the automatic transmission/reception control register (ADTC) to 1).
Figure 17-21 shows the operation timing of the bit shift detection function by the busy signal.
Figure 17-21. Operation Timing of Bit Shift Detection Function by Busy Signal
SCK1
(master)
SCK1
(slave)
SO1
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SI1
BUSY
CSIIF1
CSIE1
ERR
CSIIF1 : Interrupt request flag
CSIE1 : Bit 7 of serial operation mode register1 (CSIM1)
ERR
442
CHAPTER 17 SERIAL INTERFACE CHANNEL 1
(when BUSY0 = 1)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
: Bit 4 of automatic data transmission/reception control register (ADTC)
Bit shift due to noise
D7 D7 D6 D5 D4 D3 D2 D1
D7 D7 D6 D5 D4 D3 D2 D1
Busy not detected
D0
D0
Error interrupt request
generated
Error detected