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Symbol
7
TCL1
TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10
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Caution
If data other than identical data is to be rewritten to TCL1, the timer operation must be stopped
first.
Remarks 1. f
2. TI1 : 8-bit timer register 1 input pin
3. TI2 : 8-bit timer register 2 input pin
4. Values in parentheses apply to operation with f
208
CHAPTER 9 8-BIT TIMER/EVENT COUNTER
Figure 9-4. Timer Clock Select Register 1 Format
6
5
4
3
: Main system clock oscillation frequency
X
2
1
0
Address
FF41H
TCL13 TCL12 TCL11 TCL10
0
0
0
0
1
1
1
1
1
1
1
1
Other than above
TCL17 TCL16 TCL15 TCL14
0
0
0
0
1
1
1
1
1
1
1
1
Other than above
= 10.0 MHz.
X
When Reset
R/W
00H
R/W
8-bit Timer Register
1 Clock Selection
0
0
0
TI1 falling edge
0
0
1
TI1 rising edge
1
1
0
f
/2
2
(2.5 MHz)
X
3
1
1
1
f
/2
(1.25 MHz)
X
0
0
0
f
/2
4
(625 kHz)
X
0
0
1
f
/2
5
(313 kHz)
X
6
0
1
0
f
/2
(156 kHz)
X
0
1
1
f
/2
7
(78.1 kHz)
X
8
1
0
0
f
/2
(39.1 kHz)
X
1
0
1
f
/2
9
(19.5 kHz)
X
1
1
0
f
/2
10
(9.8 kHz)
X
12
1
1
1
f
/2
(2.4 kHz)
X
Setting prohibited
8-bit Timer Register
2 Clock Selection
0
0
0
TI2 falling edge
0
0
1
TI2 rising edge
1
1
0
f
/2
2
(2.5 MHz)
X
3
1
1
1
f
/2
(1.25 MHz)
X
4
0
0
0
f
/2
(625 kHz)
X
0
0
1
f
/2
5
(313 kHz)
X
6
0
1
0
f
/2
(156 kHz)
X
7
0
1
1
f
/2
(78.1 kHz)
X
1
0
0
f
/2
8
(39.1 kHz)
X
9
1
0
1
f
/2
(19.5 kHz)
X
10
1
1
0
f
/2
(9.8 kHz)
X
1
1
1
f
/2
12
(2.4 kHz)
X
Setting prohibited
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