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TCL
CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00
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Cautions 1. Setting of the TI0/INTP0 pin valid edge is performed by external interrupt mode register
Remarks 1. f
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT
Figure 12-3. Timer Clock Select Register 0 Format
<7>
6
5
4
(INTM0), and selection of the sampling clock frequency is performed by the sampling clock
selection register (SCS).
2. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory
manipulation instruction.
3. To read the count value when TI0 has been specified as the TM0 count clock, the value should
be read from TM0, not from the 16-bit capture register (CR01).
4. If data other than identical data is to be rewritten to TCL0, the timer operation must be stopped
first.
: Main system clock oscillation frequency
X
2. f
: Subsystem clock oscillation frequency
XT
3. TI0 : 16-bit timer/event counter input pin
4. TM0 : 16-bit timer register
5. Values in parentheses apply to operation with f
3
2
1
0
TCL03 TCL02 TCL01 TCL00
TCL06 TCL05 TCL04
CLOE
= 10.0 MHz or f
X
Address
When Reset
R/W
FF40H
00H
R/W
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
Other than above
16-bit Timer Register
Count Clock Selection
0
0
0
TI0 (Valid edge specifiable)
0
1
0
f
/2 (5.0 MHz)
X
2
0
1
1
f
/2
(2.5 MHz)
X
3
1
0
0
f
/2
(1.25 MHz)
X
Other than above
Setting prohibited
PCL Output Control
0
Output disable
1
Output enable
= 32.768 kHz.
XT
PCL Output Clock
Selection
f
(32.768 kHz)
XT
f
/2
3
(1.25 MHz)
X
4
f
/2
(625 kHz)
X
f
/2
5
(313 kHz)
X
f
/2
6
(156 kHz)
X
7
f
/2
(78.1 kHz)
X
f
/2
8
(39.1 kHz)
X
Setting prohibited
241
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