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(2) In the I
The output level of the SCK0/SCL/P27 pin is manipulated by the CLC bit of the interrupt timing specification
register (SINT).
<1> Set the serial operating mode register 0 (CSIM0) (SCL pin is set in the output mode and serial operation
<2> Manipulate the CLC bit of SINT by executing the bit manipulation instruction.
Note
Level of SCL signal is determined by the following logic in the Figure 16-52.
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Remarks 1.
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
2
C bus mode
is enabled). Set the P27 output latch to 1. While serial transfer is suspended, SCL is set to 0.
Figure 16-51. SCK0/SCL/P27 Pin Configuration
SCK0/SCL/P27
CSIM01, CSIM00 are 1, 0 or 1, 1 respectively
SCL
This figure shows the relationship between each signal and does not show the internal circuit.
2.
CLC: Bit 3 of the interrupt timing specification register (SINT)
To internal circuit
CSIE0 = 1
and
Figure 16-52. SCL Signal Logic
CLC (manipulated by the
bit manipulation instruction)
Wait request signal
Serial clock
(low level while transfer
is suspended)
Set to 1
P27
output
latch
Note
SCL
From serial clock
control circuit
407
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