NEC 78014Y Series User Manual page 510

Instruc- Mnemonic
tion
Group
8-bit XOR
Ope-
ration
CMP
16-bit ADDW
www.DataSheet4U.com
Ope- SUBW
ration CMPW
Multiply/ MULU
Divide DIVUW
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
register (PCC).
2. Clock indicates when a program is in the internal ROM area.
3. n is the number of waits when the external memory expansion area is read.
510
CHAPTER 23 INSTRUCTION SET
Operands Byte
A, #byte 2 8
saddr, #byte 3 12
A, r Note 3 2 8
r, A 2 8
A, saddr 2 8
A, !addr16 3 16
A, [HL] 1 8
A, [HL+byte] 2 16
A, [HL+B] 2 16
A, [HL+C] 2 16
A, #byte 2 8
saddr, #byte 3 12
Note 3
A, r 2 8
r, A 2 8
A, saddr 2 8
A, !addr16 3 16
A, [HL] 1 8
A, [HL+byte] 2 16
A, [HL+B] 2 16
A, [HL+C] 2 16
AX, #word 3 12
AX, #word 3 12
AX, #word 3 12
X 2 32
C 2 50
Clock
Note 1 Note 2
A ← A ∨ byte
—
(saddr) ← (saddr) ∨ byte
16
A ← A ∨ r
—
r ← r ∨ A
—
A ← A ∨ (saddr)
10
A ← A ∨ (addr16)
18 + 2n
A ← A ∨ (HL)
10 + 2n
A ← A ∨ (HL+byte)
18 + 2n
A ← A ∨ (HL+B)
18 + 2n
A ← A ∨ (HL+C)
18 + 2n
— A–byte
16 (saddr)–byte
— A–r
— r–A
10 A–(saddr)
18 + 2n A–(addr16)
10 + 2n A–(HL)
18 + 2n A–(HL+byte)
18 + 2n A–(HL+B)
18 + 2n A–(HL+C)
AX, CY ← AX+word
—
AX, CY ← AX–word
—
— AX–word
AX ← A × X
—
AX (Quotient), C (Remainder) ← AX÷C
—
CPU
Operation
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
) selected by processor clock control
Flag
AC CY
× ×
× ×
× ×
× ×
× ×
× ×
× ×
× ×
× ×
× ×
× ×
× ×
× ×