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Chapter 7
Static Memory Controller
The Static Memory Controller (SMC) is an AMBA AHB slave peripheral. The SMC inter-
faces the SoC to external memory devices.
The SMC supports four banks of external memory. Each bank has a maximum size of 16MB.
The ARM system supports 32 bits of address space. The base address of SMC-controlled
memory space is set by bits [31:28] of the address. These bits do not pass to the SMC.
Instead, the AHB arbiter uses them to identify that a system bus cycle is for the SMC.
During an external memory cycle, the bank being accessed is selected by the assertion of
the appropriate nCSx signal. The nCSx signal being asserted can be ascertained by
decoding bits [27:26]. For example, a value of '0' for these bits causes nCS0 to be
asserted, a value of '3' causes nCS3 to be asserted, and so on. Bits [23:0] are passed as
the address to the memory bank.
Base address for
memory bank
7.1 SMC Features
The SMC is programmed through the AHB. Each memory bank has its own Configuration
Register, SMCBCR[3:0]. This register allows each bank to be configured independently to:
• Support memory-mapped devices including Random Access Memory (RAM), ROM,
Flash, and burst ROM
• Vary the external bus width (8 or 16 bits wide)
• Vary the external device width (8 or 16 bits wide)
• Asynchronous Burst Mode read access to Burst Mode ROM devices
• Vary the number of wait states from 1 to 32 (independently for read and write accesses)
• Vary the number of wait states in the first access (from 1 to 32), then each subsequent
access in a burst read access from a Burst Mode ROM (from 0 to 31)
• Wait states may be extended indefinitely by an external hardware pin (nWAIT)
• Vary the bus turnaround cycles (1 to 16) allowed between a read operation and a
write operation
• Place the bank under write protection.
Table 7-1. Address Bus Organization
31:28
Chip select address space for
four memory banks
27:26
Unused
6/17/03
25:24
23:0
16MB memory bank
address space
7-1
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