Real-Time Clock
17.3.2.3 Match Register 0
MR0 is the Lower 16-bit Read/Write Match Register. Writes to this register load the lower
16-bit Match Register. Reads return the last written value.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
NOTE: The reset value of this register's bits is indeterminate.
BIT
31:16
15:0
17.3.2.4 Match Register 1
MR1 is the upper 16-bit Read/Write Match Register. Writes to this register load the Upper
16-bit Match Register; reads return the last written value.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
NOTE: The reset value of this register's bits is indeterminate.
BIT
31:16
15:0
17-6
31
30
29
28
27
—
—
—
—
—
R
R
R
R
R
15
14
13
12
11
—
—
—
—
—
RW
RW
RW
RW
RW
Table 17-7. MR0 Register Definitions
NAME
///
Reserved
RTCMR0 RTC Match Register 0 Specifies the lower 16-bit Match Register.
31
30
29
28
27
—
—
—
—
—
R
R
R
R
R
15
14
13
12
11
—
—
—
—
—
RW
RW
RW
RW
RW
Table 17-9. MR1 Register Definitions
NAME
///
Reserved
RTCMR1 RTC Match Register 1 Specifies the upper 16-bit Match Register.
LH75400/01/10/11 (Preliminary) User's Guide
Table 17-6. MR0 Register
26
25
24
23
///
—
—
—
—
R
R
R
R
10
9
8
7
RTCMR0
—
—
—
—
RW
RW
RW
RW
0xFFFE0000 + 0x08
DESCRIPTION
Table 17-8. MR1 Register
26
25
24
23
///
—
—
—
—
R
R
R
R
10
9
8
7
RTCMR1
—
—
—
—
RW
RW
RW
RW
0xFFFE0000 + 0x0C
DESCRIPTION
6/17/03
22
21
20
19
18
—
—
—
—
—
R
R
R
R
R
6
5
4
3
2
—
—
—
—
—
RW
RW
RW
RW
RW
22
21
20
19
18
—
—
—
—
—
R
R
R
R
R
6
5
4
3
2
—
—
—
—
—
RW
RW
RW
RW
RW
17
16
—
—
R
R
1
0
—
—
RW
RW
17
16
—
—
R
R
1
0
—
—
RW
RW