Pins Pd6/Int6 To Pd0/Int0 Muxing Register; Table 11-6. Pd_Mux Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

11.2.2.2 Pins PD6/INT6 to PD0/INT0 Muxing Register

PD_MUX is the Pins PD6/INT6 to PD0/INT0 Muxing Register. This register allows the sec-
ondary function of the interrupt interface pins to be configured as GPIO. The active bits
used in this register are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
Table 11-5. PD_MUX Register
31 30 29 28 27
0 0 0 0
R R R R
15 14 13 12 11
///
0 0 0 0
R R R R

Table 11-6. PD_MUX Register Definitions

BIT NAME
31:11 /// Reserved Writing to these bits has no effect. Reading returns 0.
Pin PD6/INT6/DREQ Source
00 = PD6
10:9 INT6
01 = INT6
10 = DREQ
11 = PD6
Pin PD5/INT5/DACK Source
00 = PD5
8:7 INT5
01 = INT5
10 = DACK
11 = PD5
Pin PD4/INT4/UARTRX1 Source
00 = PD4
6:5 INT4
01 = INT4
10 = UARTRX1
11 = PD4
Pin PD3/INT3/UARTTX1 Source
00 = PD3
4:3 INT3
01 = INT3
10 = UARTTX1
11 = PD3
PD2/INT2 Source
2 INT2
0 = PD2
1 = INT2
PD1/INT1 Source
1 INT1
0 = PD1
1 = INT1
PD0/INT0 Source
0 INT0
0 = PD0
1 = INT0
26 25 24 23
///
0 0 0 0 0
R R R R R
10 9 8 7
INT6 INT5
0 0 0 0 0
R RW RW RW RW
0xFFFE5000 + 0x04
DESCRIPTION
6/17/03
I/O Configuration
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
INT4 INT3 INT2 INT1 INT0
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
R R
1 0
0 0
RW RW
11-5