Table of Contents
Advertisement
Chapter 6
Memory Interface Architecture
The SHARP BlueStreak LH75400/01/10/11 devices provide the following data-path
management resources on chip:
• AHB and APB data buses
• 16KB of zero-wait-state Tightly Coupled Memory (TCM) SRAM accessible via
processor only
• 16KB of internal SRAM accessible via processor, DMA, and LCD Controller
• A Static Memory Controller with a 24-bit address, 16-bit data interface, and
four chip selects (the Static Memory Controller controls access to external memory)
• A 4-stream general purpose DMA Controller.
All system resources are memory-mapped. These include external resources, such as:
• Read Only Memory (ROM)
• Programmable ROM (PROM)
• SRAM
• External peripherals.
These also include internal resources, such as:
• System configuration registers
• Peripheral configuration registers
• TCM and internal SRAM.
The first partitioning of memory space is its subdivision into eight 'segments'. Each seg-
ment spans 512MB. The start address of each segment is fixed and determined by the
three highest order bits of the 32-bit AHB address. These segments define the type of
resource being addressed. For example:
• One segment can contain only external devices connected to the External Bus Interface.
• Another segment can contain only the internal SRAM connected to the AHB.
• Another segment is reserved for accessing the system configuration registers them-
selves, as well as many of the peripheral control registers.
• Another segment contains the TCM SRAM connected to the ARM7 local bus. This mem-
ory is only accessible via the processor and any attempt by the DMA Controller or LCD
Controller to access this segment causes a bus error to occur. See Table 6-1.
7/2/03
6-1
Advertisement
Table of Contents
