Clock And Signal Polarity Control Register; Table 13-14. Timing2 Register; Table 13-15. Timing2 Register Definitions - Sharp Blue Treak LH75400 User Manual

Color Liquid Crystal Display Controller

13.3.2.4 Clock and Signal Polarity Control Register

The Timing2 Register controls the CLCDC timing.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:27
26
25:16
15
14
13
12
11
10:6
5
4:0
13-14

Table 13-14. Timing2 Register

31 30 29 28
///
0 0 0 0
R R R R
15 14 13 12
/// IOE IPC HIS IVS
0 0 0 0
R RW RW RW RW

Table 13-15. Timing2 Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
Bypass Pixel Clock Divider
BCD
1 = Bypass the pixel clock divider logic. This is mainly used for TFT displays.
Clocks Per Line Specifies the number of actual LCDDCLK clocks to the LCD panel on
each line. This value is the number of pixels per line divided by either 1 (TFT), 4 or 8 (for
CPL
mono passive), 2-2/3 (for color passive), minus one. This must be correctly programmed in
addition to PPL for the LCD Controller to work correctly.
/// Reserved Writing to this bit has no effect. Reading returns 0.
Invert Output Enable Selects the active polarity of the output enable signal in TFT Mode.
In this mode, the LCDEN pin is used as an enable that indicates to the LCD panel when
valid display data is available. In Active Display Mode, data is driven onto the LCD data
IOE
lines at the programmed edge of LCDDCLK when LCDEN is in its active state.
0 = LCDEN output pin is active HIGH in TFT Mode.
1 = LCDEN output pin is active LOW in TFT Mode.
Invert Panel Clock Selects the edge of the panel clock on which pixel data is driven out
onto the LCD data lines.
IPC
0 = Data is driven on the LCDs data lines on the rising-edge of LCDDCLK.
1 = Data is driven on the LCDs data lines on the falling-edge of LCDDCLK.
Invert Horizontal Synchronization Inverts the polarity of the LCDLP signal.
HIS
0 = LCDLP pin is active HIGH and inactive LOW.
1 = LCDLP pin is active LOW and inactive HIGH.
Invert Vertical Synchronization Inverts the polarity of the CLFP signal.
IVS
0 = CLFP pin is active HIGH and inactive LOW.
1 = CLFP pin is active LOW and inactive HIGH.
AC Bias Pin Frequency The AC bias pin frequency is only applicable to STN displays,
which require the pixel voltage polarity to be periodically reversed to prevent damage due to
ACB DC charge accumulation. Program this field with the required value minus one to apply the
number of line clocks between each toggle of the AC bias pin (LCDEN). This field has no effect
if the CLCDC is operating in TFT Mode, when the LCDEN pin is used as a Data Enable signal.
/// Reserved Writing to this bit has no effect. Reading returns 0.
Panel Clock Divisor Derives the LCD panel clock frequency LCDDCLK from the input
CLCDC clock frequency, according to the formula LCDDCLK = CLCDCLK/(PCD + 2). For
monochrome STN displays with a 4- or 8-bit interface, the panel clock is a factor of four and
PCD
eight down on the actual individual pixel clock rate. For color STN displays, 2-2/3 pixels are
output per LCDDCLK cycle; as a result, the panel clock is 0.375 times. For TFT displays,
the pixel clock divider can be bypassed by setting the Timing2 BCD bit (bit [26]).
LH75400/01/10/11 (Preliminary) User's Guide
27 26 25 24 23
BCD
0 0 0 0 0
R RW RW RW RW
11 10 9 8 7
ACB
0 0 0 0 0
RW RW RW RW
0xFFFF4000 + 0x08
DESCRIPTION
7/15/03
22 21 20 19 18
CPL
0 0 0 0 0
RW RW RW RW RW
6 5 4 3 2
/// PCD
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RW RW
1 0
0 0
RW RW