Timing1 Register; Table 13-39. Timing1 Register; Table 13-40. Timing1 Register Definitions - Sharp Blue Treak LH75400 User Manual

Color Liquid Crystal Display Controller

13.4.5.3 Timing1 Register

The Timing1 Register is used for various delays values for output signals. All delays are
specified in number of LCD clock (LCDDCLK) periods. The active bits used in this register
are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:14
13:12
11:8
7:4
3:0
13-28

Table 13-39. Timing1 Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
/// MODDEL
0 0 0 1 0
R R RW RW RW

Table 13-40. Timing1 Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
LCDMOD LOW Delay Controls the delay (number of LCDSPS rising
MODDEL edges) to hold LCDMOD LOW before transitioning HIGH. Program
with (value required – 1). Range from 1 to 4.
CLCD-to-LCDPS Delay Controls the delay (number of LCDDCLK
periods) from the first detected LOW in horizontal sync from the CLCD
PSDEL/CLSDEL
to the falling edge of LCDPS and the rising edge of LCDCLS. Program
with (value required – 1). Range from 3 to 16.
CLCD-to-LCDREV Delay Controls the delay (number of LCDDCLK
periods) from the first detected LOW in the horizontal sync from the
REVDEL
CLCD to either edge of the generated LCDREV signal. Program with
(value required – 1). Range from 3 to 16.
CLCD-to-LCDLP Delay Controls the delay (number of LCDDCLK
periods) from the first detected LOW in the horizontal sync from the
LPDEL
CLCD to the rising edge of the generated LCDLP. Program with (value
required – 1). Range from 3 to 16.
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
PSDEL/CLSDEL
0 0 0 0
RW RW RW RW
0xFFFE4000 + 0x008
FUNCTION
7/15/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
REVDEL LPDEL
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
R R
1 0
0 0
RW RW