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LH75400/01/10/11 (Preliminary) User's Guide
21.2.3.6 Port D Data Register
PDDR is the Port D Data Register. The active bits used in this register are Read/Write.
Values written to PDDR are output on the PD pins if the corresponding PDDDR Data Direc-
tion bits are set HIGH (port output).
The values read from each bit of this register are determined by the value of the corre-
sponding bit in the Port D Data Direction Register (see Section 21.2.3.8). A read from this
register returns either:
• The last bit value written if the bit is configured as an output.
• The current value on the corresponding port input if the bit is configured as an input.
A System Reset clears all bits.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:7
6:0
31
30
29
28
0
0
0
0
R
R
R
R
15
14
13
12
0
0
0
0
R
R
R
R
Table 21-14. PDDR Register Definitions
NAME
///
Reserved Writing to these bits has no effect. Reading returns 0.
Port D Input/Output Data Specifies Port D input or output data, depend-
ing on how the value of the corresponding bit in the PDDDR Register is set
(see Section 21.2.3.8).
Port D Data
PDDDR set as output = PDDR sets the value on the GPIO Port D pins.
PDDDR set as input = PDDR reads the value on the GPIO Port D pins.
Table 21-13. PDDR Register
27
26
25
24
23
///
0
0
0
0
0
R
R
R
R
R
11
10
9
8
7
///
0
0
0
0
0
R
R
R
R
R
0xFFFDE000 + 0x04
FUNCTION
6/17/03
General Purpose Input/Output
22
21
20
19
18
0
0
0
0
0
R
R
R
R
R
6
5
4
3
2
Port D Data
0
0
0
0
0
RW
RW
RW
RW
RW
17
16
0
0
R
R
1
0
0
0
RW
RW
21-9
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