Analog-to-Digital Converter/Brownout Detector
23.3.4.5 FIFO Overrun Interrupt
The FIFO Overrun Interrupt occurs when the receiving logic tries to place data into the
FIFO after the FIFO has been completely filled, exceeding the FIFO's maximum capacity
of 16 entries. The interrupt is cleared when the FIFO is read.
23-28
AVDD
100K
AVDD
B2
AVDD
B3
AVDD
B5
AVDD
100K
PENIRQ
B13
Figure 23-5. Bias-and-Control Network Block Diagram
6/25/03
LH75400/01/10/11 (Preliminary) User's Guide
PENIRQ
B12
B4
B6
11-TO-1
B7
ANALOG
MUX
B8
A/D IN+
LH754xx-28