Port B Data Direction Register; Table 21-9. Pbddr Register; Table 21-10. Pbddr Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

21.2.3.4 Port B Data Direction Register

PBDDR is the Port B Data Direction Register. The active bits used in this register are
Read/Write.
Bits set in the PBDDR Register set the corresponding PB pin to be an output:
• Bit [5] controls pin 24 when the pin is configured as PB5. It does not control pin 24 when
the pin is configured as nWAIT.
• Bit [4] controls pin 25 when the pin is configured as PB4. It does not control pin 25 when
the pin is configured as nBLE1.
• Bit [3] controls pin 27 when the pin is configured as PB3. It does not control pin 27 when
the pin is configured as nBLE0.
• Bit [2] controls pin 28 when the pin is configured as PB2. It does not control pin 28 when
the pin is configured as nCS3.
• Bit [1] controls pin 29 when the pin is configured as PB1. It does not control pin 29 when
the pin is configured as nCS2.
• Bit [0] controls pin 30 when the pin is configured as PB0. It does not control pin 30 when
the pin is configured as nCS1.
Clearing a bit configures the pin to be an input. A System Reset clears all bits.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:6
5:0

Table 21-9. PBDDR Register

31 30 29 28 27
0 0 0 0
R R R R
15 14 13 12 11
0 0 0 0
R R R R

Table 21-10. PBDDR Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
Port B Output/Input
Port B Data Direction
Bits set = Port B output.
Bits cleared = Port B input.
26 25 24 23
///
0 0 0 0 0
R R R R R
10 9 8 7
///
0 0 0 0 0
R R R R R
0xFFFDF000 + 0x0C
6/17/03
General Purpose Input/Output
22 21 20 19
0 0 0 0
R R R R
6 5 4 3
Port B Data Direction
0 0 0 0
R RW RW RW
FUNCTION
18 17 16
0 0 0
R R R
2 1 0
0 0 0
RW RW RW
21-7