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Timers
15.2.2.8 Timer 1 Control Register
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:15
14
13
12:11 CMP1
10:9
15-18
Table 15-18. CTRL Register
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
///
PWM
TC
CMP1
0
0
0
0
0
R
RW
RW
RW
RW
Table 15-19. CTRL Register Definitions
FIELD
NAME
///
Reserved Read as zero.
PWM Output This bit allows the use of CTCMP1A as a PWM output. This is
done by properly setting up this bit as well as other bits in this register. Refer to
Section 15.1.1 for a complete explanation.
PWM
0 = Output CTCMP1A is normal and works only with the CMP1 Register.
1 = Output CTCMP1A is in PWM Mode.
Timer 1 Operation This bit determines whether Timer 1 counter is to operate
as either a free running counter or as an interval timer. When set, the counter
clears upon matching CMP1 for Timer 1. This operation is only available with the
TC
CMP1 Register for Timer 1. Refer to Section 15.1.1 for a complete explanation.
0 = Inhibit counter clear (operates as free running counter).
1 = Clear counter when CNT for Timer 1 matches CMP1 for Timer 1.
Output Value Select Sets the reference value (at which compare match
should occur) that is to be output to CTCMP1B when CNT for Timer 1 matches
the CMP1 Register for Timer 1.
00 = No change occurs to the output CTCMP1B.
01 = Output '0' to CTCMP1B.
10 = Output '1' to CTCMP1B.
11 = Toggle the output to CTCMP1B.
Output Value Select Sets the reference value (at which compare match
should occur) that is to be output to CTCMP1A when the CNT Register for Timer
1 matches the CMP0 Register for Timer 1.
CMP0
00 = No change occurs to the output CTCMP1A.
01 = Output 0 to CTCMP1A.
10 = Output 1 to CTCMP1A.
11 = Toggle the output to CTCMP1A.
LH75400/01/10/11 (Preliminary) User's Guide
26
25
24
23
22
///
0
0
0
0
R
R
R
R
R
10
9
8
7
CMP0
CAP1
0
0
0
0
RW
RW
RW
RW
RW
0xFFFC4000 + 0x30
DESCRIPTION
6/17/03
21
20
19
18
0
0
0
0
0
R
R
R
R
6
5
4
3
2
CAP0
SEL
0
0
0
0
0
RW
RW
RW
RW
17
16
0
0
R
R
1
0
CS
CCL
0
0
RW
RW
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