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LH75400/01/10/11 (Preliminary) User's Guide
13.4.2 HRTFTC Theory of Operation
All HRTFTC Control and Status Registers can be accessed through the APB. One of the
registers, the Setup Register, can be programmed to select Bypass Mode or
HR-TFT Mode.
• In Bypass Mode, LCD Controller signals are passed directly to the pins.
• In HR-TFT Mode, TFT data and control signals from the LCD Controller generate a set
of signals for driving an HR-TFT display.
Selecting HR-TFT Mode re-times the data to the falling edge of the output clock. The for-
matter also provides the:
• Features of normal scanning signals for vertical and horizontal scan
• Generation of source driver, gate driver, and voltage-preparation control signals.
The timing parameters for the HR-TFT Mode are register-programmable. When using
HR-TFT Mode, program the Setup Register first, followed by Timing registers 1 and 2.
After these registers are programmed, the LCD Controller can be enabled and the Control
Register can be used.
The HRTFTC generates the MOD signal automatically. By default, activation of MOD
occurs 2 SPS rising edge clocks after activation of the controller. This can be repro-
grammed for a longer or shorter wait, or can be overridden via the HR-TFT Control Register.
13.4.3 HRTFTC Programmer's Model
The base address for the HRTFTC is:
HRTFTC Base: 0xFFFE4000
Locations at offsets 0x010 through 0xFFF are reserved and must not be used during
normal operation.
13.4.4 HRTFTC Register Summary
NAME
Setup
CTRL
Timing1
Timing2
Table 13-34. HRTFTC Register Summary
ADDRESS
OFFSET
0x000
0x004
0x008
0x00C
///
0x010 - 0xFFF
Color Liquid Crystal Display Controller
RESET
TYPE
VALUE
RW
0x000C LCD Interface Peripheral Setup Register
RW
0x0000 LCD Interface Peripheral Control Register
RW
0x1000 LCD Interface Peripheral Timing Register 1
RW
0x0000 LCD Interface Peripheral Timing Register 2
Reserved
7/15/03
DESCRIPTION
13-25
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