LH75400/01/10/11 (Preliminary) User's Guide
15.2.2.7 Timer 0 Capture Registers
There are five CAP(n) Registers for Timer 0. They are designated:
• CAP0
• CAP1
• CAP2
• CAP3
• CAP4
Each register is a 16-bit, Read Only register. When a capture condition occurs, the con-
tents of the counter CNT are stored into the associated Capture Register. Capture Regis-
ters correspond to the input signals CTCAP0A through CTCAP0E, respectively. The edge
of the input signal used to trigger the capturing operation is determined by setting the
CMP_CAP_CTRL Register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
Table 15-16. CAP(n) Register
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
0
0
0
0
0
R
R
R
R
R
Table 15-17. CAP(n) Register Definitions
BITS FIELD NAME
31:16
///
15:0
CAP0
26
25
24
23
///
0
0
0
0
R
R
R
R
10
9
8
7
CAP0
0
0
0
0
R
R
R
R
CAP0: 0xFFFC4000 + 0x1C
CAP1: 0xFFFC4000 + 0x20
CAP2: 0xFFFC4000 + 0x24
CAP3: 0xFFFC4000 + 0x28
CAP4: 0xFFFC4000 + 0x2C
DESCRIPTION
Reserved Read as zero.
Capture Register 16-bit capture register value.
6/17/03
22
21
20
19
18
0
0
0
0
0
R
R
R
R
R
6
5
4
3
2
0
0
0
0
0
R
R
R
R
R
Timers
17
16
0
0
R
R
1
0
0
0
R
R
15-17