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LH75400/01/10/11 (Preliminary) User's Guide
Data received by the CAN Controller goes through an Acceptance Filter. The Acceptance
Filter passes to the Receive FIFO only those messages that match the ones stored in the
Acceptance Filter Registers. Acceptance filtering uses both the Acceptance Code Regis-
ters ACCR0-3 and the Acceptance Mask Registers AMR0-3. These two sets of registers
can also be used to accept either the standard frame format or the extended frame format.
The Receive FIFO is 64 bytes deep, allowing up to five full extended frame format messages.
In addition to the data bytes received, all arbitration bits and the data length code are stored
into the corresponding message object. If the FIFO has sufficient space for the data being
received, the Data Overrun Interrupt Status bit in the Status Register is set and the data frame
being received is discarded. A Data Overrun Interrupt is also generated, if enabled.
22.2.4 Time Delays
The CAN protocol can manage time delays inherent in long bus lengths. It is also efficient
at handling differences in clock frequencies for nodes on the bus. Therefore, bit timing is
very important.
The CAN standard allows bit timing to be organized into four segments to allow for
synchronization:
• A synchronization segment
• The propagation segment
• Phase segment 1
• Phase segment 2.
These segments can be organized into time blocks called 'time quantum'. The time quantum
specifies how often the bit timing is sampled to ensure that data is correct. The time quantum
is defined as a fixed amount of time that is determined by the pre-scaler and the incoming
clock frequency. The CAN Controller can break down the incoming frequency from 1 to
1/64. The segments that define the bit timing can be from 8 to 25 time quanta, according to
the CAN specification. The CAN Controller can put these timing segments into a range from
3 to 25 time quanta.
22.2.5 Bus Timing
Because bus timing is critical to the CAN protocol, the CAN Controller has two Bus Timing
Registers, BTR0 and BTR1. These registers define the specified time periods used to con-
trol the four segments.
• BTR0 defines the CAN bus time quantum.
• BTR1 defines the length of the bit period in terms of CAN bus time quanta and the point
at which the incoming data is sampled.
22.2.6 Bus Arbitration
Bus arbitration follows the CAN 2.0A and CAN 2.0B specifications. The bus is always con-
trolled by the node with the highest priority (lowest ID). Only after the bus has been
released can the next highest priority node control it.
6/17/03
Controller Area Network
22-5
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