Raw Interrupt Status Register; Table 13-24. Status Register; Table 13-25. Status Register Definitions - Sharp Blue Treak LH75400 User Manual

Color Liquid Crystal Display Controller

13.3.2.9 Raw Interrupt Status Register

Status is the Raw Interrupt Status Register. This register is Read/Write.
• On a read, this register returns five bits that may generate interrupts when set.
• On writes to this register, a bit value of '1' clears the interrupt corresponding to that bit.
Writing a '0' has no effect.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:5
4
3
2
1
0
13-20

Table 13-24. Status Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
R R R R R

Table 13-25. Status Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
Master Bus Error Interrupt Asserted when an ERROR response is
received by the master interface during a transaction with a slave. When an
MBERROR
ERROR response is encountered, the master interface enters an error state
until it receives a signal that the error has been cleared.
Vertical Compare Interrupt Asserted when one of four vertical display
regions, selected via [13:12] of the LCD Control Register, is reached (see
VCOMP
Section 13.3.2.8). The interrupt can be made to occur at the start of Vertical
Synchronization, Back Porch, Active Video, and Front Porch.
LCD Next Base Address Update Interrupt Asserted when either the
UPBASE or the LPBASE values are transferred to the UPCURR or
LNBU LPCURR incrementer, respectively. This indicates to the system that it can
safely update the UPBASE or the LPBASE Register with new frame base
addresses if required.
FIFO Underflow Interrupt Asserted when internal data is requested from
an empty LCD DMA FIFO. Internally, individual upper and lower panel LCD
FUF
DMA FIFO Underflow Interrupt signals are generated and this is the single
combined version of these.
/// Reserved Writing to this bit has no effect. Reading returns 0.
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23 22
///
0 0 0 0 0
R R R R R
10 9 8 7 6
///
0 0 0 0 0
R R R R R
0xFFFF4000 + 0x20
DESCRIPTION
7/15/03
21 20 19 18 17
0 0 0 0 0
R R R R R
5 4 3 2 1
FUF
0 0 0 0 0
R RC RC RC RC
16
0
R
0
///
0
R