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LH75400/01/10/11 (Preliminary) User's Guide
16.3.1 WDT Register Definitions
16.3.1.1 Control Register
CTRL is the Control Register. The active bits used in this register are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:8
7:4
3
2
1
0
Table 16-2. CTRL Register
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
///
0
0
0
0
0
R
R
R
R
R
Table 16-3. CTRL Register Definitions
///
Reserved Writing to these bits has no effect. Reading returns 0.
Time Out Period Selects 1 of 16 possible values to load into the counter to de-
termine the time-out period. Example: 0x0 = 2
TOP
setting or changing the time-out period, the new value will not come into affect un-
til a counter-reset command has been issued or when the WDT times out.
Freeze EN Bit (set-only)
0 = Do not stop the EN bit from being cleared when the watchdog is enabled.
FRZ
1 = Stop the EN bit from being cleared when the watchdog is enabled. This
avoids accidental write operations that disable the watchdog, and can only be
cleared by a System Reset.
///
Reserved Writing to these bits has no effect. Reading returns 0.
Time-out Response Determines the output response on a time-out period.
0 = Only a System Reset is generated on a time-out period.
RSP
1 = An interrupt is generated on the first time-out period. If this is not cleared, a
System Reset is generated on the second time-out period.
Watchdog Enable/Disable
0 = Watchdog disabled. Counter does not decrement, and no interrupts or
System Resets will be generated by the watchdog.
EN
1 = Watchdog enabled. Allows the counter to decrement, causing interrupts to be
generated if the count is not periodically reset to stop the count value from
reaching zero.
26
25
24
23
22
///
0
0
0
0
0
R
R
R
R
R
10
9
8
7
6
0
0
0
0
0
R
R
R
RW
RW
0xFFFE3000 + 0x00
DESCRIPTION
6/17/03
Watchdog Timer
21
20
19
18
0
0
0
0
R
R
R
R
5
4
3
2
TOP
FRZ
///
0
0
0
0
RW
RW
RW
R
16
31
, 0xF = 2
HCLK cycles. When
17
16
0
0
R
R
1
0
RSP
EN
0
0
RW
RW
16-3
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