General Status Register; Table 20-49. Gsr Register; Table 20-50. Gsr Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

20.3.2.20 General Status Register

Register Bank: 1
GSR is the General Status Register. The GSR Register reflects all pending block-level
interrupt requests. Each bit in the GSR Register reflects the status of a block and can be
individually enabled by the GER Register (see Section 20.3.2.5). The GER Register
masks-out GIR interrupts; it does not affect the GSR Register bits. To mask-out the bits in
GSR so they do not appear in GSR, mask them out at a lower level.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:6
5
4
3
2
1
0
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
R R R R R

Table 20-50. GSR Register Definitions

/// Reserved Do not modify. Read as zero.
Timers Interrupt Request Indicates that a timer has expired. See
TIR
Section 20.3.2.14.
Transmit Machine Interrupt Request Indicates that the transmit machine is
TXIR
either empty or disabled/idle.
/// Reserved Read as zero.
Receiver Interrupt Request Generates the receiver interrupt. Servicing of the
RXIR
interrupt is defined by the RST Register (see Section 20.3.2.17).
Tx FIFO Interrupt Request Indicates that FIFO occupancy is equal to or below
TFIR
the threshold.
Receive FIFO Interrupt Request Indicates that Rx FIFO occupancy is
RFIR
above threshold.

Table 20-49. GSR Register

26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
///
0 0 0 0
R R R R
0xFFFC2000 + 0x1C
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
TIR TXIR /// RXIR TFIR RFIR
0 0 1 0 0
R R R R R
UART2
17 16
0 0
R R
1 0
1 0
R R
20-31