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UART2
20.1 UART2 Features
UART2 provides the following features:
• Supports baud rates up to 3,225,600 baud (given a system clock of 70 MHz)
• Support for 5, 6, 7, 8, or 9 data bits per character
• Even, odd, HIGH, LOW, software, or no parity-bit generation and detection
• 3/4, 1, 1-1/4, 1-1/2, 1-3/4, or 2 stop-bit generation
• µLAN address flag
• Full-duplex operation
• Separate transmit and receive FIFOs, with programmable depth (1 or 4). Each FIFO has
the following programmable-service 'trigger levels' and overrun protection:
– Receive trigger levels: 1/4, 1/2, 3/4, or full
– Transmit trigger levels: empty, 1/4, 1/2, 3/4.
• Two 16-bit baud-rate generators. Each baud-rate generator can be configured as a timer
and is completely independent of the other. The mode, output, and source of each baud-
rate generator are configurable.
• A single interrupt that can be triggered by transmit and receive FIFO thresholds, receive
errors, control character or address marker reception, or timer timeout
• Generation and detection of breaks during UART transactions
• Support for local loopback, remote loopback, and auto-echo modes
• µLAN Address Mode.
20.2 UART2 Theory of Operation
All Control and Status Registers for the UART can be accessed through the APB.
During transmission, data is written into the transmit FIFO through the APB interface. If the
UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the LCR Register. Data continues to be transmitted until there is no data left in the trans-
mit FIFO. The TxSt bit in the LSR Register is set to '0' as soon as data is written to the
transmit FIFO. The TxSt bit remains LOW until the FIFO is empty and the last character,
including the stop bits, has been sent.
NOTE: Once data transmission begins, wait at least one baud cycle before turning off the transmission.
20-2
LH75400/01/10/11 (Preliminary) User's Guide
6/17/03
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