LH75400/01/10/11 (Preliminary) User's Guide
17.3.2.2 Data Register 1
DR1 is the Upper 16-bit Read Data Register. Reads from this register return the value of
the upper 16 bits of the counter when DR0 was last accessed. The DR0 Register should
be read before reading the DR1 Register to avoid the mismatch between the DR0 and the
DR1 Registers due to a counter rollover.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
NOTE: The reset value of this register's bits is indeterminate.
BIT
31:16
15:0
31
30
29
28
27
—
—
—
—
—
R
R
R
R
R
15
14
13
12
11
—
—
—
—
—
R
R
R
R
R
Table 17-5. DR1 Register Definitions
NAME
///
Reserved
RTC Data Register 1 Specifies the upper 16-bit counter value from when
RTCDR1
DR0 was last accessed.
Table 17-4. DR1 Register
26
25
24
23
///
—
—
—
—
R
R
R
R
10
9
8
7
RTCDR1
—
—
—
—
R
R
R
R
0xFFFE0000 + 0x04
DESCRIPTION
6/17/03
Real-Time Clock
22
21
20
19
18
—
—
—
—
—
R
R
R
R
R
6
5
4
3
2
—
—
—
—
—
R
R
R
R
R
17
16
—
—
R
R
1
0
—
—
R
R
17-5