Clcdc Registers; Tftc Registers; Table 26-7. Clcdc Register Summary; Table 26-8. Hrtftc Register Summary - Sharp Blue Treak LH75400 User Manual

System-on-chip preliminary
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LH75400/01/10/11 (Preliminary) User's Guide

26.7 CLCDC Registers

Base address: 0xFFFF4000
NAME
Timing0
Timing1
Timing2
///
UPBASE
LPBASE
INTRENABLE
Ctrl
Status
Interrupt
UPCURR
LPCURR
///
Palette
///
NOTE: These registers pertain to the LH75401 and LH75411 SoC devices only.
26.8 HR-TFTC Registers
Base address: 0xFFFE4000
NAME
Setup
CTRL
Timing1
Timing2
///
NOTE: These registers pertain to the LH75401 and LH75411 SoC devices only.

Table 26-7. CLCDC Register Summary

ADDRESS
TYPE
OFFSET
RW
0x000
0x00000000 Horizontal Timing Panel Control Register
0x004
RW
0x00000000 Vertical Timing Panel Control Register
0x008
RW
0x00C
RW
0x010
RW
0x014
RW
0x00000000 Lower Panel Frame Buffer Base Address Register
0x018
RW
0x00000000 Interrupt Enable Register
0x01C
RW
0x020
RW
0x00000000 Raw Interrupt Status Register
0x024
R
0x00000000 Final Masked Interrupts Register
0x028
R
0x00000000
0x02C
R
0x00000000
0x030 - 0x1FC
0x200 - 0x3FC
RW
0x400 - 0x7FF

Table 26-8. HRTFTC Register Summary

ADDRESS
TYPE
OFFSET
0x000
RW
0x004
RW
0x008
RW
0x00C
RW
0x010 - 0xFFF
6/17/03
RESET
VALUE
0x0000000 Clock and Signal Polarity Control Register
Reserved
0x0000000 Upper Panel Frame Buffer Base Address Register
LCD Panel Parameters, LCD Panel Power, and
0x0000
CLCDC Control Register
Upper Panel Frame Buffer Current Address
Register
Lower Panel Frame Buffer Current Address
Register
0x00000
Reserved
256 × 16-bit Color Palette Register. Palette is
addressed at 32 bits.
Reserved
RESET
VALUE
0x000C LCD Interface Peripheral Setup Register
0x0000 LCD Interface Peripheral Control Register
0x1000 LCD Interface Peripheral Timing Register 1
0x0000 LCD Interface Peripheral Timing Register 2
Reserved
Register Map
DESCRIPTION
DESCRIPTION
26-7

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Blue treak lh75401Blue treak lh75410Blue treak lh75411

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