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UART0 and UART1
19.1 UART0 and UART1 Features
UART0 and UART1 provide the following features:
• Supports baud rates up to 921,600 baud (given an external crystal frequency of
14.756 MHz)
• Support for 5, 6, 7, or 8 data bits per character
• Even, odd, stick, or no-parity bit generation and detection
• 1 or 2 stop-bit generation
• Full-duplex operation
• Separate transmit and receive FIFOs, with programmable-service 'trigger levels' (1/8,
1/4, 1/2, 3/4, and 7/8) and overrun protection
• Programmable baud-rate generator that enables the UART input clock to be divided by
16 to 65535x16. It also generates an internal clock that is common to both transmit and
receive portions of the UART. The divisor can be a fractional number.
• Support for Direct Memory Access (DMA)
• Support for generating and detecting breaks during UART transactions
• Loopback testing.
A UART clock that can operate asynchronously or synchronously with the system clock.
19.2 UART0 and UART1 Theory of Operation
All UART Control and Status Registers can be accessed through the APB. During trans-
mission, data writes to the transmit FIFO through the APB interface. When data writes to
the transmit FIFO:
• The UART causes the data frame to start transmitting with the parameters indicated in
register LCR_H if the UART is enabled. Data continues to transmit until no data remains
in the transmit FIFO.
• The BUSY bit in the FR Register is asserted. This bit remains HIGH until the transmit
FIFO is empty and the last character, including the stop bits, has been sent.
19.2.1 UART0 and UART1 Receiver Data Frame
A UART receiver data frame has the following structure:
• A start bit that indicates the beginning of the frame. This bit consists of a 0 on the
receiver input for one bit period.
• Data, which consists of five to eight data bits.
• An optional parity bit, which can be used with available hardware for parity-error
checking.
• One or more stop bits, which indicate the end of the frame. Stop bits consist of a 1 on
the receiver input for as many bit periods as the number of stop bits specified when pro-
gramming the receiver.
19-2
LH75400/01/10/11 (Preliminary) User's Guide
7/15/03
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