Ahb Clock Control Register; Table 9-22. Ahbclkctrl Register; Table 9-23. Ahbclkctrl Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

9.3.2.10 AHB Clock Control Register

AhbClkCtrl is the AHB Clock Control Register. When writing to this register, setting a data
bit to one stops the AHB DMA clock. Bit [1] of this register should never be cleared. The
bit used in this register is Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:9
8:2
1
0

Table 9-22. AhbClkCtrl Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 9-23. AhbClkCtrl Register Definitions

FIELD NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
/// Read as 0, always write 0 to these bits.
/// Reads as 1, always write 1 to this bit.
AHB DMA Clock
DMA
0 = AHB DMA clock is running.
1 = Stops the AHB DMA clock.
Reset, Clock, and Power Controller
26 25 24 23 22
///
0 0 0 0 0
R R R R R
10 9 8 7 6
0 0 0 0 0
R R RW RW RW
0xFFFE2000 + 0x2C
DESCRIPTION
7/15/03
21 20 19 18 17
0 0 0 0 0
R R R R R
5 4 3 2 1
/// ///
0 0 0 0 1
RW RW RW RW RW
16
0
R
0
DMA
1
RW
9-15