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LH75400/01/10/11 (Preliminary) User's Guide
10.1 Theory of Operation ..................................................................................... 10-1
10.2 VIC Programmer's Model ............................................................................. 10-7
9.3.1 RCPC Register Summary ......................................................................... 9-6
9.3.2 RCPC Register Definitions ........................................................................ 9-7
9.3.2.1 Control Register.................................................................................. 9-7
9.3.2.2 Identification Register ......................................................................... 9-8
9.3.2.3 Remap Control Register ..................................................................... 9-8
9.3.2.4 Soft Reset Register ............................................................................ 9-9
9.3.2.5 Reset Status Register....................................................................... 9-10
9.3.2.6 Reset Status Clear Register ............................................................. 9-11
9.3.2.7 HCLK Prescaler Register ................................................................. 9-12
9.3.2.8 Peripheral Clock Control Register 0 ................................................. 9-13
9.3.2.9 Peripheral Clock Control Register 1 ................................................. 9-14
9.3.2.10 AHB Clock Control Register ........................................................... 9-15
9.3.2.11 LCD Clock Prescaler Register........................................................ 9-16
9.3.2.12 SSP Clock Prescaler Register........................................................ 9-17
9.3.2.13 External Interrupt Configuration Register ....................................... 9-18
9.3.2.14 External Interrupt Clear Register .................................................... 9-20
10.1.1 Interrupts ............................................................................................... 10-1
10.1.2 VIC Interrupt Listing............................................................................... 10-2
10.1.3 Vectored Interrupts ................................................................................ 10-3
10.1.4 External Interrupts ................................................................................. 10-3
10.1.5 Clearing Interrupts ................................................................................. 10-4
10.1.6 Priority ................................................................................................... 10-4
10.1.7 Sequencing ........................................................................................... 10-5
10.1.8 External Level-Sensitive Interrupts........................................................ 10-7
10.1.9 Software Guidelines .............................................................................. 10-7
10.2.1 VIC Register Summary.......................................................................... 10-8
10.2.2 VIC Register Definitions ........................................................................ 10-9
10.2.2.1 IRQ Status Register........................................................................ 10-9
10.2.2.2 FIQ Status Register ...................................................................... 10-10
10.2.2.3 Raw Interrupt Status Register ...................................................... 10-11
10.2.2.4 Interrupt Select Register............................................................... 10-12
10.2.2.5 Interrupt Enable Register.............................................................. 10-13
10.2.2.6 Interrupt Enable Clear Register .................................................... 10-14
10.2.2.7 Software Interrupt Register........................................................... 10-15
10.2.2.8 Software Interrupt Clear Register ................................................. 10-16
10.2.2.9 Vector Address Register............................................................... 10-17
10.2.2.10 Default Vector Address Register ................................................ 10-18
10.2.2.11 Vector Address Registers........................................................... 10-19
10.2.2.12 Vector Control Registers ............................................................ 10-20
6/17/03
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