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Timers
15.2.2 Timer Register Definitions
15.2.2.1 Timer 0 Control Register
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS FIELD NAME
31:5
4:2
1
0
15-10
Table 15-4. CTRL Register
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
0
0
0
0
0
R
R
R
R
R
Table 15-5. CTRL Register Definitions
///
Reserved Read as zero.
Count Clock Select Specifies the system count clock.
000 = System clock/2
001 = System clock/4
010 = System clock/8
011 = System clock/16
SEL
100 = System clock/32
101 = System clock/64
110 = System clock/128
111 = CTCLK
The CS field (bit [1]) must be clear for changes to the SEL field to take effect.
Start/Stop Counter 0 Specifies whether counter 0 is stopped or started.
0 = Stops counter 0
CS
1 = Starts counter 0
This bit must be cleared for changes to the SEL bit (bit [2]) to take effect.
For more information, see Section 15.1.1.
Counter 0 Clear Writes a 1 to clear the contents of timer 0 to 0x0000.
CCL
Write operations of 0 are ignored. This bit always reads as zero and is
reset to 0 as the counter is cleared.
LH75400/01/10/11 (Preliminary) User's Guide
26
25
24
23
22
///
0
0
0
0
R
R
R
R
R
10
9
8
7
///
0
0
0
0
R
R
R
R
R
0xFFFC4000 + 0x00
DESCRIPTION
6/17/03
21
20
19
18
0
0
0
0
0
R
R
R
R
6
5
4
3
2
SEL
0
0
0
0
0
R
RW
RW
RW
17
16
0
0
R
R
1
0
CS
CCL
0
0
RW
RW
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