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Liquid Crystal Display Controller
14.2.1 LCD DMA FIFOs
The upper and lower LCD DMA FIFOs can be independently controlled to cover single-
and dual-panel LCD types. Each FIFO is 16 words deep by 32 bits wide. In single-panel
STN Mode, the LCD DMA FIFOs are made to appear as a single FIFO of twice the size.
Synchronization logic is used to transfer the pixel data from the AHB system clock domain,
which controls the LCD DMA FIFO, to the LCDDCLK domain. The LCDDCLK is a separate
clock provided by the RCPC. The water level marks within each FIFO are set such that each
FIFO requests data when at least four locations become available. An interrupt signal is
asserted if an attempt is made to read either of the two LCD DMA FIFOs when they are empty.
14.2.2 Pixel Serializer
The pixel serializer reads the 32-bit-wide LCD data from the output port of the LCD DMA
FIFO and extracts 4, 2, or 1 bpp data, depending on the operating mode. In Dual Panel
Mode, data is alternately read from the upper and lower LCD DMA FIFOs. Depending on
the operating mode, the extracted data is used to point to a grayscale value in the palette
RAM or is directly applied to a LCD panel input.
14.2.3 How Pixels are Stored in Memory
Table 14-1 and Table 14-2 show the data structure in each DMA FIFO word corresponding
to the bpp combinations; where a pixel p(x) is encoded in the bit field for pixels displayed
in the order (x = 0, 1, 2, 3...). The required data for each panel display pixel must be
extracted from the data word.
bpp
1
p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16
2
4
bpp
1
2
4
14-4
Table 14-1. DMA FIFO Output Bits [31:16]
31
30
29
28
27
p15
p14
1
0
1
0
1
p7
3
2
1
0
3
Table 14-2. DMA FIFO Output Bits [15:0]
15
14
13
12
p15
p14
p13
p12
p7
p6
1
0
1
0
p3
3
2
1
0
LH75400/01/10/11 (Preliminary) User's Guide
DMA FIFO OUTPUT BITS
26
25
24
23
p13
p12
p11
0
1
0
1
p6
2
1
0
3
DMA FIFO OUTPUT BITS
11
10
9
8
p11
p10
p9
p8
p5
p4
1
0
1
0
p2
3
2
1
0
6/17/03
22
21
20
19
p10
p9
0
1
0
1
p5
2
1
0
3
7
6
5
4
3
p7
p6
p5
p4
p3
p3
p2
p1
1
0
1
0
1
p1
3
2
1
0
3
18
17
16
p8
0
1
0
p4
2
1
0
2
1
0
p2
p1
p0
p0
0
1
0
p0
2
1
0
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