Upper Panel Frame Buffer Base Address Register; Table 14-13. Upbase Register; Table 14-14. Upbase Register Definitions - Sharp Blue Treak LH75400 User Manual

Liquid Crystal Display Controller

14.3.2.5 Upper Panel Frame Buffer Base Address Register

The UPBASE Register is one of two LCD DMA Base Address Registers (the other is
LPBASE). Together with LPBASE, this Read/Write register programs the base address of
the frame buffer.
UPBase is used for:
• Single-panel STN displays
• The upper panel of dual-panel STN displays.
UPBase (and LPBase for dual panels) must be initialized before enabling the LCDC.
Optionally the value can be changed mid-frame to allow double-buffered video displays to
be created. These registers are copied to the corresponding current registers at each LCD
vertical synchronization. This event causes the LNBU bit and an optional interrupt to be
generated. The LNBU bit indicates that it is safe to update both the UPBASE and LPBASE
Registers. The interrupt can be used to reprogram the base address when generating
double-buffered video.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:2 LCDUPBASE
1:0
14-12

Table 14-13. UPBASE Register

31 30 29 28 27
0 0 0 0 0
RW RW RW RW RW
15 14 13 12 11
0 0 0 0 0
RW RW RW RW RW

Table 14-14. UPBASE Register Definitions

NAME
LCD Upper Panel Base Address Specifies the starting address of the
upper-panel frame data in memory and is word aligned.
/// Reserved Writing to these bits has no effect. Reading returns 0.
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23 22
LCDUPBASE
0 0 0 0 0
RW RW RW RW RW
10 9 8 7 6
LCDUPBASE
0 0 0 0 0
RW RW RW RW RW
0xFFFF4000 + 0x10
DESCRIPTION
6/17/03
21 20 19 18 17
0 0 0 0 0
RW RW RW RW RW
5 4 3 2 1
0 0 0 0 0
RW RW RW RW R
16
0
RW
0
///
0
R