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UART0 and UART1
19.2.3 On-Chip DMA Capabilities
UARTs 0 and 1 can be programmed to utilize the on-chip DMA to reduce processor band-
width required to service UART activities. DMA functions support burst transfers on the
receive channel, transmission channel, or both.
• When DMA is enabled on the receive channel, a DMA request is issued when the
receive FIFO reaches its programmed high water mark. Once the DMA block services
the request, a new one is issued when the FIFO fills above its high water mark.
• When DMA is enabled on the transmit channel, a request is issued when the transmit
channel FIFO falls below its low water mark. The request is reissued if the FIFO remains
below that level when the DMA request has been serviced, or the next time that the FIFO
falls below that level.
DMA requests are masked when the UART issues an error interrupt. If the UART is in the
FIFO Disabled Mode, only the DMA Single Transfer Mode can operate, since only one
character can be transferred to or from the FIFOs at any time. As a result, the programmed
water mark level is not relevant in the FIFO Disabled Mode.
19.2.4 Programming Control Registers
The UART must be disabled before any of the Control Registers are programmed. When
the UART is disabled in the middle of transmission or reception, it completes the operation
on the current character before stopping.
19-4
LH75400/01/10/11 (Preliminary) User's Guide
7/15/03
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