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LH75400/01/10/11 (Preliminary) User's Guide
9.3.2 RCPC Register Definitions
Except where noted, all registers are both writable and readable. Writing other than the
default values to any reserved location and bit can cause the system to malfunction.
9.3.2.1 Control Register
Ctrl is the Control Register. The active bits used in this register are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:10
9
8
7
6:5
4:2
1:0
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
///
0
0
0
0
0
R
R
R
R
R
Table 9-4. Ctrl
FIELD NAME
Reserved Writing to these bits has no effect. Reading returns 0.
///
Lock
0 = All RCPC registers accessible through the APB, other than this bit and
LOCK
the IntClear Register (see Section 9.3.2.14), are write-protected.
1 = All RCPC APB-accessible registers are write-enabled (default).
///
Reserved Writing to these bits has no effect. Reading returns 0.
Reserved Read as zero. Always write zero. Writing a 1 causes
///
unpredictable results.
///
Reserved
Power Down Mode Select
000 = Active Mode
001 = Standby Mode
010 = Sleep Mode
011 = Stop1 Mode
PWR DWN SEL
100 = Stop2 Mode
Other values = undefined
Be sure there are no transmit or receive operations occurring when the
LH75400/01/10/11 SoC device enters Standby, Sleep, Stop1, or Stop2
Mode. These bits always read 000 because the RCPC clears them au-
tomatically at wakeup.
///
Reserved Read as 1. Always write 1.
Reset, Clock, and Power Controller
Table 9-3. Ctrl Register
26
25
24
23
///
0
0
0
0
R
R
R
R
10
9
8
7
///
///
0
1
0
0
R
RW
R
RW
0xFFFE2000 + 0x00
Register Definitions
DESCRIPTION
7/15/03
22
21
20
19
18
0
0
0
0
0
R
R
R
R
R
6
5
4
3
2
///
PWR DWN SEL
1
1
0
0
0
R
R
RW
RW
RW
17
16
0
0
R
R
1
0
///
1
1
RW
RW
9-7
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