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UART2
20.3.2.17 Receive Machine Status Register
Register Bank: 1
RST is the Receive Machine Status Register. The RST Register displays the status of the
receive machine. It reports events that occurred since the RST was cleared.
All RST Register contents, except bit [0], are cleared when it is read. Each bit in this register,
when set, can cause an interruption. Five bits of this register are shared with the LSR Register
When this register is read, the read operation clears bits [7:0] of this register and bits [4:0]
of the LSR Register. Similarly, these same bits in the RST and LSR Registers are cleared
when the LSR Register is read.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7
6
5
4
3
2
1
0
20-28
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
///
0
0
0
0
0
R
R
R
R
R
Table 20-44. RST Register Definitions
NAME
///
Reserved Do not modify. Read as zero.
Control/Address Character Received
1 = Causes an interrupt if a control character or address character is received.
CRF
In µLAN Mode, this interrupt indicates that an address character has been received. In
Normal Mode, this interrupt indicates that a standard ASCII or EBCDIC control character
has been received.
Programmed Control/Address Character Received
1 = Causes an interrupt when an address or control character match occurs.
PCRF
In µLAN Mode, this interrupt indicates that an address character has been received. In
Normal Mode, this interrupt indicates that a standard ASCII or EBCDIC control character
has been received.
BKT
Break Terminated Indicates that a break condition has been terminated.
BKD
Break Detected Indicates that a break condition has been detected.
FE
Framing Error Indicates that a received character did not have a valid stop bit.
PE
Parity Error Indicates that a received character had a parity error.
OE
Overrun Error Indicates that a received character was lost because the Rx FIFO was full.
Receive FIFO Interrupt Request Functionally identical to the RFIR bit of the GSR Reg-
ister. Indicates that the RX FIFO level is above the Rx FIFO threshold. This bit is forced
RIFR
LOW during any READ from the Rx FIFO. A zero written to this bit acknowledges an Rx
FIFO interrupt.
LH75400/01/10/11 (Preliminary) User's Guide
Table 20-43. RST Register
26
25
24
23
///
0
0
0
0
R
R
R
R
10
9
8
7
CRF
0
0
0
0
R
R
R
R
0xFFFC2000 + 0x14
DESCRIPTION
6/17/03
22
21
20
19
18
0
0
0
0
0
R
R
R
R
R
6
5
4
3
2
BKT
BKD
FE
PE
0
0
0
0
0
R
R
R
R
R
.
17
16
0
0
R
R
1
0
OE
RFIR
0
0
R
R
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