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LH75400/01/10/11 (Preliminary) User's Guide
10.1.8 External Level-Sensitive Interrupts
When external interrupts are configured as level-sensitive, the ISR must ensure that there
is a sufficient time between the time when the source of the external interrupt is cleared
and the time when the interrupt at the VIC is cleared. Otherwise, the source of an external
interrupt can pull the line HIGH or LOW (depending on whether the external interrupt input
pin is configured as active LOW or active HIGH) before the interrupt is cleared at the VIC.
Because the VIC samples the line after the clear, it generates another interrupt to the ARM
core if the line is recognized to be still active. To avoid this situation, clear the source of
the interrupt as early as practical in the ISR. Doing so ensures a maximum delay between
clearing the external interrupt and clearing the interrupt at the VIC.
An interrupt line shared by multiple open-collector devices in a wired-OR configuration with
a pull-up resistor can be extremely susceptible to causing multiple interrupts if there is
insufficient delay between the time when the source of the external interrupt is cleared and
the time when the interrupt at the VIC is cleared. This situation is due to the relatively slow
risetime of the interrupt signal when being pulled to its inactive state by the pull-up resistor.
The larger the resistor and load capacitance on the interrupt line, the slower the rise time
and the greater the delay required.
10.1.9 Software Guidelines
User software that makes changes to the VIC IRQStatus, FIQStatus, or RawIntr register
should not immediately be followed by a read to these registers. Instead, at least one Idle
cycle must separate the write and read operations. The Idle cycle(s) is necessary because
the VIC is a zero-wait-state peripheral that requires two clocks for the write operation to
update internal registers. The pipelining of the AHB, along with the VIC not inserting wait
states, means that a read access immediately following a write returns the previous regis-
ter values.
10.2 VIC Programmer's Model
The base address for the VIC is:
VIC Base Address: 0xFFFFF000
The following locations are reserved and must not be used during normal operation:
• Locations at offsets 0x020
• Locations at offsets 0x300
• Locations at offsets 0x304
• Locations at offsets 0x308
• Locations at offsets 0x30C
• Locations at offsets 0x310
6/17/03
Vectored Interrupt Controller
10-7
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