Fiq Status Register; Table 10-5. Fiqstatus Register; Table 10-6. Fiqstatus Register Definitions - Sharp Blue Treak LH75400 User Manual

Vectored Interrupt Controller

10.2.2.2 FIQ Status Register

FIQStatus is the FIQ Status Register. This Read Only register provides the status of the
interrupts after FIQ masking.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:0 FIQStatus
10-10

Table 10-5. FIQStatus Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
R R R R R

Table 10-6. FIQStatus Register Definitions

NAME
Interrupt Status After Masking Shows the status of the interrupts after
masking by the IntEnable and IntSelect Registers.
0 = Interrupt is not active.
1 = Interrupt is active and generates an FIQ exception to the ARM7TDMI-S core.
Bits [31:0] correspond to the interrupt order in the Interrupt Assignments Table
(See Table 10-1).
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23 22
FIQStatus
0 0 0 0
R R R R R
10 9 8 7
FIQStatus
0 0 0 0
R R R R R
0x004
0xFFFFF000 +
DESCRIPTION
6/17/03
21 20 19 18
0 0 0 0 0
R R R R
6 5 4 3 2
0 0 0 0 0
R R R R
17 16
0 0
R R
1 0
0 0
R R