Receive Status/Error Clear Register; Table 19-4. Rsr/Ecr Register (Write Operations); Table 19-5. Rsr/Ecr Register Definitions (Write Operations) - Sharp Blue Treak LH75400 User Manual

UART0 and UART1

19.3.1.2 Receive Status/Error Clear Register

RSR/ECR is the Receive Status Register/ Error Clear Register.
If the status is read from this register, the status bits in this register correspond to the status
bits of the last word read from the DR Register. The status information for overrun is set
immediately when an overrun condition occurs.
A write to the ECR Register clears the framing, parity, break, and overrun errors. All bits
clear to '0' on System Reset.
NOTE: The received data character must be read first from the DR Register before reading the error status
Table 19-4 and Table 19-5 describe the RSR/ECR Register for write operations.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
19-8
associated with that data character from the RSR Register. This read sequence cannot be reversed
because the RSR Register is updated only when a read occurs from the DR Register. However, the
status information can also be obtained by reading the DR Register.

Table 19-4. RSR/ECR Register (Write Operations)

31 30 29 28
0 0 0 0
R R R R
15 14 13 12
///
0 0 0 0
R R R R

Table 19-5. RSR/ECR Register Definitions (Write Operations)

NAME
/// Reserved Do not modify. Read as zero.
Error Clear1 A write to this register clears the framing, parity, break,
ERROR CLEAR
and overrun errors. The data value is not important.
LH75400/01/10/11 (Preliminary) User's Guide
27 26 25 24 23
///
0 0 0 0 0
R R R R R
11 10 9 8 7
0 0 0 0 0
R R R R W
UART0: 0xFFFC0000 + 0x004
UART1: 0xFFFC1000 + 0x004
DESCRIPTION
7/15/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
ERROR CLEAR
0 0 0 0 0
W W W W W
17 16
0 0
R R
1 0
0 0
W W